Semiconductor Engineering

A Comprehensive Approach To System-Level ESD

The performance and reliability of an electronics system largely depend on the system’s immunity from an electrostatic discharge (ESD) event. Because the components, custom chips and package come from ...
Semiconductor Engineering

Shock Value

Chip-Package-System (CPS) ESD simulation enables system-wide ESD robustness validation, a common challenge in automotive and aerospace applications. To enable CPS ESD analysis requires an accurate ...
Electronic Design

Is System-Level ESD Testing Valid for ICs?

Electronic system designs often include transient protection to ensure system robustness for electrostatic discharge (ESD) events. Adding external ESD protection without compromising system I/O speed, ...
EDN

Transistor level ESD verification in large SoC designs

When it comes to large system-on-chip (SoC) designs, there is a need for a comprehensive electrostatic discharge (ESD) verification flow that can verify both topological and geometrical constructions ...