EDN

RTL Analysis and Optimization Platform

Atrenta Inc., a provider of SoC Realization solutions for the semiconductor and consumer electronics industries, announced the 5.0 release of its SpyGlass RTL analysis and optimization platform. This ...
Semiconductor Engineering

Power Optimization: What’s Next?

Concerns about the power consumed by semiconductors has been on the rise for the past couple of decades, but what can we expect to see coming in terms of analysis and automation from EDA companies, ...
EDN

Calypto Delivers Industry’s First RTL Power Analyzer Based on Sequential Analysis Technology

SANTA CLARA, Calif. –– August 24, 2009 –– Calypto® Design Systems Inc. (www.calypto.com) today announced it has developed the industry’s most accurate register-transfer level (RTL) power analysis ...
Electronic Design

Optimize For Power Before RTL Synthesis To Ease Timing Closure

Power consumption is a primary design consideration for today's systems-on-a-chip (SoCs). Consequently, pervasive powerreduction techniques are now an established part of the design process from ...
Nasdaq

Synopsys Unveils RTL Architect To Accelerate Design Closure

The RTL Architect product represents the industry's first physically aware RTL analysis, optimization, and signoff system built on a fast, multi-dimensional prediction engine for superior RTL handoff ...
Semiconductor Engineering

Power Issues Rising For New Applications

Managing power in chips is becoming more difficult across a wide range of applications and process nodes, forcing chipmakers and systems companies to rethink their power strategies and address ...
Electronic Design

Sequential Power Optimization Tool Pinpoints Clock-Gating Opportunities At RTL

Unlike combinational power reduction tools, PowerPro CG identifies and generates sequential clock-gating transformations. It fits into existing design flows with industry-standard library, timing, and ...