EDN

Physical RTL optimization solves problems early

While most of the ASIC industry is focused on solving timing and congestion problems at the netlist level, LSI Logic has developed and deployed an innovative methodology to resolve these physical ...
EDN

RTL Analysis and Optimization Platform

Atrenta Inc., a provider of SoC Realization solutions for the semiconductor and consumer electronics industries, announced the 5.0 release of its SpyGlass RTL analysis and optimization platform. This ...
Design-Reuse

Calypto Extends Industry Lead in RTL Power Optimization

SANTA CLARA, Calif. – June 8, 2010 – Calypto Design Systems Inc., the leader in sequential analysis technology, today announced the release of PowerPro 4.0, the latest version of the industry’s ...
Nasdaq

Synopsys Unveils RTL Architect To Accelerate Design Closure

The RTL Architect product represents the industry's first physically aware RTL analysis, optimization, and signoff system built on a fast, multi-dimensional prediction engine for superior RTL handoff ...
Electronic Design

Reduce Power in Chip Designs with Sequential Clock Gating

Clock gating is one of the most frequently used techniques in RTL to reduce dynamic power consumption without affecting the functionality of the design. One method involves inserting gating conditions ...
Semiconductor Engineering

Does SoC Signoff Mean More Than RTL?

As the cost of failure continues to rise, SoC engineers see the growing importance of ensuring their work is as correct as possible as soon as possible in the design process. They cannot afford to ...
Semiconductor Engineering

Does EDA Consider RTL Power Optimization As Job Done?

The “Power Buzz” leading into this year’s Design Automation Conference was around System Level Power Architecture and Optimization—some would say the natural progression of EDA towards the next big ...