EDN

Synthesis tool links MATLAB with ASIC, FPGA designs

MILPITAS, Calif. — AccelChip has crafted a DSP synthesis tool that converts algorithms developed in MATLAB into synthesizable RTL that can be used during the design of FPGAs, ASICs and structured ...
Business Wire

MathWorks Speeds FPGA and ASIC Verification with Universal Verification Methodology (UVM) Support

NATICK, Mass.--(BUSINESS WIRE)--MathWorks today announced that HDL Verifier provides support for the Universal Verification Methodology (UVM) starting with Release 2019b, which is currently available.
EDN

An FPGA-to-ASIC case study for refining smart meter design

Many embedded system designs are first implemented using FPGAs. This may be for quicker prototyping or to provide a platform for software development. Sometimes, the FPGAs will remain in the design ...
mccormick.northwestern.edu

COMP_ENG 355: ASIC and FPGA Design

This course will introduce students to practical design methodologies for developing applications for FPGAs and ASICs. You will learn the fundamentals for FPGA and ASIC design through software coding ...
Design-Reuse

Structured ASIC Based SoC Design

Complex System-on-Chip (SoC) designs are fast becoming commonplace in today’s applications. Hardware designers must overcome many complex and challenging issues regarding cost, time-to-market (TTM), ...
Design-Reuse

FPGA to ASIC Strategy for Communication SoC Designs

Current communication systems utilize highly complex SoC designs for numerous applications. Hardware designers must overcome many complex and challenging issues regarding cost, time-to-market, ...
Semiconductor Engineering

FPGA And System Designs Get To Market Faster Leveraging ASIC-Proven Analysis Tools

Digital systems need clocks. Today’s designs require more from clocking schemes than ever before, and it’s likely this trend will continue. Increasing power constraints have resulted in finer-grained ...
Electronics Weekly

Taking the road from ASIC to FPGA

Guest columnist Tom Feist, director of tools marketing at Xilinx restates the arguments for considering FPGAs – no DFM, no mask prep, no DRC/LVS If you’ve been in the electronics industry even just a ...
Electronic Design

Faraday Showcases FPGA-Go-ASIC, SONOS eFlash, and eFPGA Solutions

This article appeared in Microwaves & RF and has been published here with permission. Check out our Design Automation Conference 2023 coverage. Faraday Technology comes to Booth 2343 at DAC to discuss ...
Semiconductor Engineering

FPGA Design Tradeoffs Getting Tougher

FPGAs are getting larger, more complex, and significantly harder to verify and debug. In the past, FPGAs were considered a relatively quick and simple way to get to market before committing to the ...